| 摘要 |
To manufacture a wafer level stack package, first and second wafers having first and second via patterns are prepared. The second wafer is attached to the first wafer such that the front sides of the first and second wafers face each other and the first and second via patterns are connected to each other. The back side of the second wafer is ground and etched such that the lower ends of the second via patterns are exposed and projected. The back side of the first wafer is ground and etched such that the lower ends of the first via patterns are exposed and projected. A chip level stack structure is formed by sawing a wafer level stack structure having the stacked wafers into a chip level. The chip level stack structure is attached to a substrate having electrode terminals.
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