| 摘要 |
A method for locking a phase and an apparatus therefore is provided to reduce a gate count by unification of integral block. A phase locked loop includes a multi-phase clock signal generation unit(550), an analog/ digital converter(510), a phase detector(520), a control signal generation unit(600), and a voltage controlled oscillator(540). The multi-phase clock signal generates n multi-phase clock from a clock. The analog/digital converter generates n-multi phase input signal from the input signal corresponding to n multi-phase clock signal. The phase detector generates n error signals corresponding to n-multi-phase input signal. The control signal generation unit generate one of n- multi error signals in response to the clock. The voltage controlled generation unit generates a new clock by the control signal.
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