发明名称 |
Integrated circuit with embedded identification code |
摘要 |
An integrated circuit (100) has a plurality of inputs (110) and a plurality of outputs (120). In a test mode, a test arrangement including a plurality of logic gates (140) is coupled between the plurality of inputs (110) and the plurality of outputs (120). The logic gates from the plurality of logic gates (140) have a first input coupled to an input of the plurality of inputs (110) and a further input coupled to a fixed logic value source (150). The fixed logic value source (150) is used to define an identification code of the integrated circuit (100), which can be retrieved at the plurality of outputs (120) when an appropriate bit pattern is fed to the plurality of inputs (110).
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申请公布号 |
US7506227(B2) |
申请公布日期 |
2009.03.17 |
申请号 |
US20050525598 |
申请日期 |
2005.02.25 |
申请人 |
NXP B.V. |
发明人 |
VAN DE LOGT LEON MARIA ALBERTUS;DE JONG FRANCISCUS GERARDUS MARIA |
分类号 |
G01R31/28;G01R31/3173;G01R31/3185;G11C29/36;H01L21/822;H01L27/04;H03K19/21 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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