| 发明名称 | Hetergeneous processor apparatus and method | ||
| 摘要 | A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software. | ||
| 申请公布号 | US9448829(B2) | 申请公布日期 | 2016.09.20 |
| 申请号 | US201213730491 | 申请日期 | 2012.12.28 |
| 申请人 | INTEL CORPORATION | 发明人 | Narvaez Paolo;Srinivasa Ganapati N.;Gorbatov Eugene;Subbareddy Dheeraj R.;Naik Mishali;Naveh Alon;Prabhakaran Abirami;Weissmann Eliezer;Brett Paul;Hahn Scott D.;Herdrich Andrew J.;Khanna Gaurav;Fenger Russell J.;Bigbee Bryant E.;Henroid Andrew D.;Koufaty David A. |
| 分类号 | G06F9/00;G06F9/455;G06F9/50;G06F9/38 | 主分类号 | G06F9/00 |
| 代理机构 | Nicholson De Vos Webster & Elliott LLP | 代理人 | Nicholson De Vos Webster & Elliott LLP |
| 主权项 | 1. A processor comprising: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; and virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software. | ||
| 地址 | Santa Clara CA US | ||