| 摘要 |
A synchronous semiconductor memory device can perform an internal operation for an input address with reliability regardless of the frequency of a system clock. The semiconductor memory device includes an internal operation detecting unit for generating a flag signal in response to internal command signals; a delay unit for delaying the flag signal for a programmed time; and an enable signal generating unit for generating an enable signal activated in response to a transition timing of the flag signal and inactivated in response to a transition timing of the delayed flag signal, wherein an internal address derived from an external address is transferred to a core area while the enable signal is activated.
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