| 摘要 |
PROBLEM TO BE SOLVED: To enable a microcomputer which executes two or more levels of tasks to execute other processing, when it accesses a low-speed device, without waiting for completion of the access execution. SOLUTION: A bus interface 10 has a plurality of access channels 11, 12 and 13 corresponding respectively to two or more levels of tasks to be executed on the microcomputer side. Each access channel has a plurality of registers a-e. When a shared memory access request is generated during execution of an optional task on the microcomputer side, access is requested to the access channel according to the level of this task. Namely, the request content is set to the register of the access channel. When the setting is completed, the bus interface 10 immediately turns ON DRY signal (releases WAIT). Thereafter, a bus access control part 15 executes shared memory access processing. COPYRIGHT: (C)2009,JPO&INPIT
|
