| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce overhead related to data transfer error processing in a command chain. <P>SOLUTION: This processor comprises a CPU 20 capable of executing a predetermined arithmetic processing, a memory 30 accessible by the CPU, and a data transfer mechanism 40 capable of controlling the data transfer between it and the memory instead of the CPU. The data transfer mechanism comprises a command chain section for continuously transferring data by execution of a preset command chain, and a retry control section for executing the retry processing when a transfer error occurs in data transfer in the command chain section. By reporting a command related to the transfer error to the CPU after the completion of the execution of the command chain, the interruption frequency for error processing is reduced, and the system performance is improved. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
