| 摘要 |
<p>A DMOS transistor and a manufacturing method thereof are provided to reduce an area of the device while maintaining a breakdown voltage by forming a draft region vertically. A P type or N type well region(102) is formed on a semiconductor substrate(101) through an impurity ion implantation. A drift region(103) is formed on the semiconductor substrate with a well region. A trench is formed on the semiconductor substrate inside the drift region. A gate oxide layer(106) and a gate electrode(107) are formed in the trench. A source/drain region(108) is formed by implanting the same conductive impurity as the drift region to both substrates of the gate electrode.</p> |
