| 摘要 |
There provided is a semiconductor device comprising at least a two or more-stage CMOS inverter coupled circuits using an SGT with high integration and a high speed. The semiconductor device comprises the CMOS inverter coupled circuit with n (n is two or more) CMOS inverters coupled. Each of the n inverters has a pMOS SGT, an nMOS SGT, an input terminal that is wired to connect the gate of the pMOS SGT to the gate of the nMOS SGT, an output terminal that is wired to connect a drain diffusion layer of the pMOS SGT to the drain diffusion layer of the nMOS SGT in an island-like semiconductor lower layer, a power supply wiring for the pMOS SGT wired on the source diffusion layer of the pMOS SGT, and a power supply wiring for the nMOS SGT wired on the source diffusion layer of the nMOS SGT. The n-1st output terminal is connected with the nth input terminal. |
