| 摘要 |
PROBLEM TO BE SOLVED: To provide an SRAM enabling the cell size thereof to be reduced. SOLUTION: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies (P<SB>1</SB>, P<SB>2</SB>) formed by laminating a lower semiconductor layer (drain) 57, an intermediate semiconductor layer 58 and an upper semiconductor layer (source) 59, and gate electrodes 66 formed on side walls of the laminate (P<SB>1</SB>, P<SB>2</SB>) with gate insulating films 63 interposed therebetween. In each vertical MISFET, the lower semiconductor layer 57 constitutes a drain, the intermediate semiconductor layer 58 constitutes a substrate (channel region), and the upper semiconductor layer 59 constitutes a source. The lower semiconductor layer 57, the intermediate semiconductor layer 58 and the upper semiconductor layer 59 are each comprised of a silicon film. The lower semiconductor layer 57 and the upper semiconductor layer 59 are doped a p-type and constituted of a p-type silicon film. COPYRIGHT: (C)2009,JPO&INPIT
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