| 摘要 |
PROBLEM TO BE SOLVED: To reduce the circuit scale of a display driving circuit. SOLUTION: A data line driving circuit 5 is provided with a control part 11, a graphic memory (RAM) 14, an address decoder 15, a read circuit 16, a write circuit 18, a switch 20, an address decoder 21, an AND circuit 22, a sampling circuit 23, a selector circuit 24, a line memory 25, an output part 26, an address data bus 13, a read data bus 17, and a CPU/RGB common data bus 19. A CPU port and an RGB port include the CPU/RGB common data bus 19, the switch 20, the address decoder 21, and the AND circuit 22 in common. The read circuit 16 is common to the CPU port and an LCD port. The line memory 25 is common to the RGB port and the LCD port. A column address for moving image data is produced in an address producing circuit 12 to receive a start signal STH and a clock signal CLK. COPYRIGHT: (C)2009,JPO&INPIT
|
