CHIP TESTER, CHIP TEST SYSTEM, CHIP TEST SETUP, METHOD FOR IDENTIFYING AN OPEN-LINE FAILURE AND COMPUTER PROGRAM

摘要

A chip tester (110) for testing a plurality of devices under test (130,132) comprises an input (140) for connection to a common line (142), a bias source (152) for biasing the common line and a controller (160). The controller is adapted to control a provision of a first signal (166) for a first DUT and a provision of a second signal (168) for a second DUT, to control the first DUT and the second DUT such that, in a measurement phase, the effect of an electrical characteristic of the first DUT to the DC state at the input is distinguishable from the effect of an electrical characteristic of the second DUT to the DC state at the input. A measurement unit (144) is adapted to measure a DC state at the input in the measurement phase. A diagnosis unit (150) is adapted to decide whether an open-line failure is present with respect to the first DUT on the basis of the measured DC state at the input.