发明名称 Conditional execute bit in a graphics processor unit pipeline
摘要 An arithmetic logic stage in a graphics processor unit includes a number of arithmetic logic units (ALUs). An instruction is applied to sets of operands comprising pixel data associated with different pixels. The value of a conditional execute bit determines how the pixel data in a set of operands is processed by the ALUs.
申请公布号 US2009046105(A1) 申请公布日期 2009.02.19
申请号 US20070893620 申请日期 2007.08.15
申请人 BERGLAND TYSON J;OKRUHLICA CRAIG M 发明人 BERGLAND TYSON J.;OKRUHLICA CRAIG M.
分类号 G09G5/00;G06T15/00 主分类号 G09G5/00
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