Memory device has floating transistor which causes bipolar junction operation to flow by applying read current and data stored at memory cell is connected to selected source line

摘要

A memory array has several memories cells which have a floating transistor. The floating transistor has an emitter E (14), collector C (16) and gate G (22) are connected to a bit line, a source line and a word line, respectively. A row control unit performs refresh operation in response to refresh command from external device are internal control circuit by selecting a source line and a bit line. A read current causes bipolar junction operation to flow from transistor when data stored at memory cell is connected to the selected source and bit lines. Independent claims are included for the following: (1) memory cell structure; (2) method for controlling refresh operation; and (3) capacitor-less memory device.