| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a storage circuit capable of reducing the number of transistors per memory cell by sharing a reading circuit in an SRAM, and reducing a maximum current and preventing electromigration by using slow charging based on adiabatic charging. <P>SOLUTION: An SRAM circuit includes two inverters, flip-flops FF for receiving each other's output, and transfer transistors N<SB>3</SB>and N<SB>4</SB>for transmitting signals to bit lines BL and BLi_N. In this case, A signal read from a memory cell during reading is entered to a gate of an nMOSFET(N<SB>6</SB>) having a source grounded, and a circuit having a drain of the nMOSFET(N<SB>6</SB>) and the bit line BL_N grounded by an nMOSFET(N<SB>7</SB>) is shared by a plurality of memory cell lines Line<SB>1</SB>to Line<SB>N</SB>. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
