发明名称 |
INTEGRATED METHOD OF FABRICATING A MEMORY DEVICE WITH REDUCED PITCH |
摘要 |
Provided is a method of fabricating a memory device. A substrate including an array region and a peripheral region is provided. A first feature and a second feature are formed in the array region. The first feature and the second feature have a first pitch. A plurality of spacers abutting each of the first feature and the second feature are formed. The plurality of spacers have a second pitch. A third feature in the peripheral region and a fourth and fifth feature in the array region are formed concurrently. The forth and fifth feature have the second pitch. |
申请公布号 |
US2009035902(A1) |
申请公布日期 |
2009.02.05 |
申请号 |
US20070831031 |
申请日期 |
2007.07.31 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
XU JEFF J.;YEN ANTHONY;HSIEH CHIA-TA;CHUNG CHIA-CHI;LIN CHENG-MING |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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