| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To prevent designing/verification TAT of a semiconductor integrated circuit from increasing while taking pattern dependency of transistor characteristics into sufficient consideration. <P>SOLUTION: The designing method for the semiconductor integrated circuit includes a step (A) of generating layout data on the semiconductor integrated circuit and a step (B) of generating mask data based upon the layout data. The step (B) includes a step (B1) of extracting parameters defining a layout pattern of a periphery of an object transistor included in the semiconductor integrated circuit by referring to the layout data, wherein the parameters include at least a width of an element separation structure of the periphery of the object transistor; a step (B2) of correcting a gate length and a gate width of the object transistor so as to cancel variation in characteristic of the object transistor from a design value depending upon the extracted parameters; and a step (B3) generating the mask data from the layout data having the gate length and gate width corrected. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
