| 摘要 |
A multi port phase change memory device capable of improving access performance ability of memory cell is provided to perform write operation and read operation by using a plurality of ports. A memory cell comprises a first NMOS transistor and a second NMOS transistor(T-P1, T-P2) driven by two word lines and phase change material. A first word line(WL-P1) and a first bit line(BL-P1) are connected to a first port. A second word line(WL-P2) and a second bit line(BL-P2) are connected to a second port. The first NMOS transistor is connected to the first word line, the first bit line, and the phase change material. The second NMOS transistor is connected to the second word line, the second bit line, and the phase change material. One side electrode of the phase change material is commonly connected to a source terminal of the first and the second NMOS transistors, and forms a storage node. The other side electrode of the phase change material is connected to a source line.
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