| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the time to transfer a count value between circuits which have clock signals with different frequency. <P>SOLUTION: In count signals CNT to CNT3 of a gray code counter 11 which is operated by a transmitting side clock signal CLKA, a changed bit position is detected to output bit position signals BIT0 to BIT3, and also a decoder 12 is provided to output the count signal whose the bit position is changed as a bit value signal BIT. Further, this bit value signal BIT is delayed by two clocks by a receiving side clock signal CLKB to be transferred as a count value CN together with the count signals of other unchanged bit positions. Thus, a receiving side buffer is not required and the time to transfer the count value can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
