发明名称 |
Iterative turbo decoder with single memory |
摘要 |
The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
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申请公布号 |
US7480846(B2) |
申请公布日期 |
2009.01.20 |
申请号 |
US20040514288 |
申请日期 |
2004.11.12 |
申请人 |
ST WIRELESS SA |
发明人 |
CHARPENTIER SEBASTIEN;VALDENAIRE PATRICK |
分类号 |
H04L13/00;G06F5/00;H03M13/27;H03M13/29;H04L1/00 |
主分类号 |
H04L13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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