发明名称 High speed array pipeline architecture
摘要 A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.
申请公布号 US7480202(B2) 申请公布日期 2009.01.20
申请号 US20080072125 申请日期 2008.02.22
申请人 MICRON TECHNOLOGY, INC. 发明人 VO HUY;INGALLS CHARLES
分类号 G11C8/00 主分类号 G11C8/00
代理机构 代理人
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