| 摘要 |
<p>A wafer (2) comprises a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer (2), first and second saw lines (4, 5) separating the integrated circuits (1), and a plurality of process control modules (6) formed on the wafer (2). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows, and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y) defined by the columns. The plurality of process control modules (6) are formed on the wafer (2) such that a given process control module (6) of the plurality of process modules (6) is bounded by two consecutive first saw lines (4), is bounded by two consecutive second saw lines (5), or is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).</p> |
