| 摘要 |
PROBLEM TO BE SOLVED: To provide a method and device for performing access to a cache memory in a processor. SOLUTION: The requested valid address of requested data is used for performing access to the requested data in one or more level 1 caches of a processor. When one or more level 1 caches of the processor do not include the requested data corresponding to the requested valid address, the requested valid address is translated into an actual address. The look aside buffer includes one corresponding entry with respect to each cache line in each of one or more level 1 caches of the processor. The corresponding entry shows translation from the valid address into the actual address with respect to the cache line. The translated actual address is used for performing access to a level 2 cache. COPYRIGHT: (C)2009,JPO&INPIT |
