发明名称 AUTOMATIC DELAY ADJUSTMENT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make versatility more excellent than a method following a manual. SOLUTION: A computer 1 performs processing (S2) for adding dummy wiring 50-J to layout data 7 and processing (S4) for connecting dummy wiring 50-J to object wiring 40 between a cell 30-1 and a cell 30-2 as timing violation in the layout data 7. In the processing (S4), the computer 1 replaces the dummy wiring 50-J with a dummy wiring cell 60 having pins 61 and 62 corresponding to the both ends of the dummy wiring 50-J (S12), and cuts the object wiring 40, and generates object wiring 41 and 42 (S13), and connects the object wiring 41 and 42 to pins 61 and 62 (S14 to S16), and replaces the dummy wiring cell 60 with the dummy wiring 50-J to set wiring where the dummy wiring 50-J is connected to the cut section of the object wiring 40 (S17). COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009009247(A) 申请公布日期 2009.01.15
申请号 JP20070168218 申请日期 2007.06.26
申请人 NEC ELECTRONICS CORP 发明人 MIYAGAWA SEIJI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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