| 摘要 |
A semiconductor memory apparatus for reducing test time is provided to reduce the number of a channel for the chip test by adding a control circuit with a test signal. In a semiconductor memory apparatus for reducing test time, an input buffer controller is comprised of the control signal supply(120) and input buffer controller(100). An input buffer controller is operated by a write driver driving signal(ENWTDIN) which is generated according to the write command. An input buffer controller outputs a buffer control signal(DQSIN) by amplifying the difference of signal with a control signal composed of the pair of the first and two signals. The first signal is directly inputted to the input buffer controller, and the second signal is inputted through the control signal supply unit to the input buffer controller. A control signal supply transmits the second signal to the input buffer controller. The control signal supply unit transmits the reference voltage(VREF) to the input buffer controller as the second signal(DQSB). |
