<p>The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.</p>
申请公布号
WO2009003139(A1)
申请公布日期
2008.12.31
申请号
WO2008US68425
申请日期
2008.06.26
申请人
CADENCE DESIGN SYSTEMS, INC.;WHITE, DAVID;SCHEFFER, LOUIS K.