<p>A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect may maintain transaction path order to support outstanding transactions to multiple targets while maintaining transaction ordering; maintain request path order; maintain response path order; interleave channels in an aggregate target with unconstrained burst sizes; have configurable parameters for channels in an aggregate target and mapping of address regions onto the one or more aggregate targets; chop individual transactions whose data address sequence within that transaction crosses an interleaved channel address boundary in an aggregate target; chop individual 2-Dimensional (2D) transactions that cross channel boundaries headed for channels in an aggregate target so that two or more of the chopped portions retain their 2D burst attributes, as well as implement many other internal controls.</p>
申请公布号
WO2009002998(A1)
申请公布日期
2008.12.31
申请号
WO2008US68107
申请日期
2008.06.25
申请人
SONICS, INC.;WINGARD, DREW E.;CHOU, CHIEN-CHUN;HAMILTON, STEPHEN W.;SWARBRICK, IAN ANDREW;VAKILOTOJAR, VIDA
发明人
WINGARD, DREW E.;CHOU, CHIEN-CHUN;HAMILTON, STEPHEN W.;SWARBRICK, IAN ANDREW;VAKILOTOJAR, VIDA