| 摘要 |
Lookup table circuits (LUTS) having multiple stages differently optimized to balance delays through the lookup table. A first multiplexing stage is optimized for a fast path from the control input to the data outputs, while a second and subsequent stage multiplexers are optimized for a fast path from data inputs to data outputs. In some embodiments, additional delay is introduced into the control inputs of the later stages, e.g., the LUT input paths with the smallest through-delays, in order to further balance the through-delays for the lookup table.
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