| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To resolve the problem that a state that a common bus is not accessed by any bus master is reduced and an effect of clock gating is small in the case that a clock gating technology of busses is introduced in a computer system provided with a plurality of processors. <P>SOLUTION: In a computer system 101, a plurality of bus systems 201 each of which includes a transmission/reception circuit 204, a buffer circuit 203, a routing circuit 202, an address information able 210, a clock input circuit 205, an external output bus 211, and data input/output buses 206, 207, 208, and 209 having an N-bit width are disposed among a CPU 102, a processor 103 for exclusive use, and a memory 104, and a clock is supplied to only a bus system which data passes, whereby power consumption is reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
