| 摘要 |
<P>PROBLEM TO BE SOLVED: To generate a bit clock synchronized with an input variety mirror encoded signal by a simple circuit arrangement. <P>SOLUTION: A local clock CLK (13.56 MHz) is supplied to a master counter&edge window generating portion 113 as a count clock. A bit frequency of an input variety mirror encoded signal MCS is 106 kHz. A generating portion 113 generates edge detection windows EDW0 and EDW1 of a predetermined range before and after counted values 0 and 64. An edge detection output DED in the windows EDW0 and EDW1 clears reset counters 114 and 115, and the reset counters 114 and 115 output reset pulses REP0 and REP1 corresponding to a starting position of a bit period of the signal MCS and clears a master counter. A bit clock BCK, etc., obtained based on the counted value includes the one synchronized with the signal MCS. The circuit includes simpler circuit arrangement, compared with the conventional one for obtaining a bit clock using analog PLL (phase locked loop) circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT |
