发明名称 FRAME SYNCHRONOUS CIRCUIT
摘要 PURPOSE:To enable to reduce the frame synchronism return time remarkably, by adding the memory circuit in n bits storing the agreement and disagreement discrimination output of the frame synchronism pattern. CONSTITUTION:The frame synchronism circuit consists of the n-bit shift register 21, n digital counter 23, OR gate 24, and AND gates 25, 26 (range surrounded in broken lines). The result of discrimination as to the frame synchronism position at each frame pulse position, i.e., the output of the OR gate 27 is stored in the register 21, and the result of discrimination stored 21 is read out at the next frame pulse position and compared with the result of detection of the pattern detection circuit 12 and FF17 is reset with the agreement (set in case of disagreement). Further, as to the frame further before the previous frame, the result of detection of agreement and disagreement with the frame synchronism pattern is used, allowing to reduce the synchronism return time.
申请公布号 JPS55125747(A) 申请公布日期 1980.09.27
申请号 JP19790033607 申请日期 1979.03.22
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 KOU MASAHIRO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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