发明名称 FORMING METHOD OF FLAT WIRING LAYER
摘要 PURPOSE:To make possible multi-layer of wiring layer of IC by making into a flat wiring layer having nearly the same level of the upper surface, an insulation layer having a reversed pattern of wiring pattern adjacent to the side of a desired pattern on an insulation substrate, and a surface that includes the upper surface of the insulation layer. CONSTITUTION:A reversed pattern consisting of an insulation layer I1 on an insulaion layer A and Pt layer Q1, Q2 are formed. After forming a photo resist layer T1 over the entire surface, the insulation layer I1, and Pt layer Q1 are exposed by ashing the entire surface and the resist layer is removed leaving only the insulation layer I1 and the Pt layer Q1. A heat treatment after forming a poly Si layer U1 over the entire surface forms a wiring layer W1 consisting of Pt silicide by reaction with the Pt layer Q1. When the unreacted poly Si layer U1 is removed, the surface F1 of the insulation layer I1 and the surface H1 of the wiring layer W1 are made on the same level.
申请公布号 JPS57134951(A) 申请公布日期 1982.08.20
申请号 JP19810021301 申请日期 1981.02.16
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 YASHIRO TAKEHISA
分类号 H01L21/3205;(IPC1-7):01L21/88 主分类号 H01L21/3205
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