| 摘要 |
PURPOSE:To connect secondary stations having various processing performance to the same circuit by providing a primary station with a means for varying a data transmission speed in accordance with the performance of the secondary station for a data transmission which follows an HDLC controlling procedure. CONSTITUTION:In an initial state, a primary station 1 and a secondary station 2 operate by a transmission clock having a basic speed and when a processor is enabled to operate in normal answer mode, a response signal UA is transmitted from the processor 21 to the primary station 1 through a transmitting buffer 23, a transmission circuit 22, and a circuit 7 and then stored in a receiving buffer 14 through a transmitting circuit 22. When a command RR is transmitted from a processor 11 to the secondary station 2, the processor 21 sends a response signal including a discrimination signal to the primary station 1. The primary station 1 stores the discrimination information in a prescribed area of a table 15 and supplies a speed controlling signal 17 having contents which corresponds to the discrimination information to a transmission controlling circuit 16 to indicate the switching of transmission clocks. The processor 21, on the other hand, indicates the switching of clocks by a transmission controlling circuit 25 after the transmission of said response signal I. |
