发明名称 ERROR INTERRRUPTING SYSTEM
摘要 PURPOSE:To suitably recover the error of a channel device, by providing an error interruption from the channel device to a CPU with the control of a service processor, in an error interruption system for a computer system. CONSTITUTION:A data transfer device is respectively provided between channel devices 31, 32,...3n and a service processor 4. The processor 4 sequentially scans the devices 31, 32...3n and a monitors the error of each channel device. If an error takes place in any channel, the processor 4 analyzes the content of the error for required error recovery processing. If the recovery of error is impossible, the forced interruption processing section of the error channel to inform the error and the state of channels of content of error to a CPU1 is started and the error interruption from the error channel to the CPU1 is provided.
申请公布号 JPS581249(A) 申请公布日期 1983.01.06
申请号 JP19810098380 申请日期 1981.06.26
申请人 FUJITSU KK 发明人 HIHARA MASAHITO;OKADA TATSUO
分类号 G06F9/48;G06F11/07;G06F13/00 主分类号 G06F9/48
代理机构 代理人
主权项
地址