发明名称 DATA SAMPLING CIRCUIT
摘要 PURPOSE:To always secure a slice level automatically without having readjustment when the data level has a change, by collating a prescribed binary code given previously with the output of the 1st slicer and delivering a detecting pulse only when the coincidence is obtained with Fleming's code. CONSTITUTION:The reversible counters 24a and 24b connected to the 1st and 2nd switching circuits 20a and 20b start the reversing count from the maximum value and on the basis of the synchronizing pulse which is separated from the received digital data. According to this count value, the 1st voltage having its varied level is generated by D/A converters 25a and 25b. The 1st voltage deivered from the converters 25a and 25b respectively is applied to the 1st slicers 27a and 27b of the upper and lower limit detecting circuits 26a and 26b and collated with the binary signal applied to a terminal set previously. Then the detecting pulses are applied to the circuits 20a and 20b from Fleming's code detecting circuits 28a and 28b only when the coincidence is obtained from the above-mentioned collation. Thus a slice level is always secured automatically and then delivered from a slicer 30 without having readjustment in accordance with the upper and lower limit values.
申请公布号 JPS58114682(A) 申请公布日期 1983.07.08
申请号 JP19810213149 申请日期 1981.12.28
申请人 SHIN NIPPON DENKI KK 发明人 INOSE TETSUO
分类号 H04N7/025;H04N5/44;H04N7/03;H04N7/035;H04N7/08;H04N7/081 主分类号 H04N7/025
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