| 摘要 |
PURPOSE:To process PAL signals with a simple subtraction or addition and to obtain the synchroinzing signal of PAL accurately and easily, by processing the offset component at each horizontal period specific to the PAL signal digitally. CONSTITUTION:A clock CP4 four times the chrominance subcarrier frequency fsc is applied to a horizontal address counter 2 from a reference signal forming circuit 1 and a pulse having 2 fH of frequency is applied to a vertical address counter 3. A line discrimination signal from the counter 3 is applied to a phase sfifter 4 and a readout control circuit 5 and a signal different from the phase by 90 deg. from a phase shifter 4 is applied to a wave shape ROM 9. A type discriminating signal from the circuit 5 is applied to a burst gate signal generating circuit 6 and a data ROM 7, and the offset component at each horizontal period is processed digitally by using an operation circuit 8, the ROM 9 and a digital filter 10. The synchronizing signal of PAL is outputted accurately by processing it with a simple subtraction or addition. |
