发明名称 SORTING AND MERGING CIRCUIT
摘要 PURPOSE:To shorten an arithmetic time through a simple constitution, by comparing two data by the comparator of a cell and storing them in the settling register or the bubble register of the next stage according to the compared result. CONSTITUTION:(m) Unit cells are arranged successively, an input bus 2 is connected to the cells 1, and (m) flag registers 3 supplied with input flag signals when data are inputted to the respective cells 1 are arranged. The selector 7 of the 1st cell selects the data of the settling register 6 where data is stored temporarily when an input flag is 0 or selects data from the bus 2 when the input flag 1 is 1, sending it to the comparator 9. The comparator 9 compares the selected data with the data of the HL register 4 to store larger data in a register 6 and smaller data in the bubble register 8 of the next-stage cell. The 2nd and succeeding cells compare 9 data selected by selectors 7 with data in registers 8 to store larger data in registers 6 and smaller data in registers 8 of next- stage cells, sorting data inputted successively.
申请公布号 JPS5922138(A) 申请公布日期 1984.02.04
申请号 JP19820130760 申请日期 1982.07.27
申请人 SUMITOMO DENKI KOGYO KK;TABATA KOUICHI 发明人 WADA YUTAKA;TABATA KOUICHI;OONO YUTAKA;OOKAWA YOSHINORI
分类号 G06F12/00;G06F7/24 主分类号 G06F12/00
代理机构 代理人
主权项
地址