| 摘要 |
PURPOSE:To improve the speed of the amplifying operation of a dynamic type RAM and reduce noises in the earthed wire of the circuit, by dividing a sense amplifier and operating only one sense amplifier of a set containing a selected data line at an early timing. CONSTITUTION:Address signals ai-ai<-2> are inputted into NOR gate circuits G1-G3, respectively, in prescribed combinations and output signals of the NOR gate circuits G1-G3 are inputted into one side inputs of AND gate circuits G4- G6. A timing signal phi of a timing which is earlier than the operation timing signal phipa1 of a sense amplifier is commonly upon the other inputs of the AND gate circuits G4-G6. Output signals of these AND gate circuits G4-G6 are supplied to one side inputs of OR gate circuits G7-G9, respectively, and a timing signal phipa3 of a timing which is later than the operation timing signal phipa2 of a sense amplifier is impressed upon the other inputs of the OR gates G7-G9. Then each timing signal phi1-phi8 which controls switching MOS FETs Q10, Q11, Q16, Q17, etc., installed to each sense amplifier is obtained from the OR gate circuits G7-G9. |
