| 摘要 |
PURPOSE:To accelerate the operation of a CMOS circuit and to reduce the power consumption of the CMOS by forming a substrate bias generating circuit in a semiconductor integrated circuit device having the CMOS circuit as an element and supplying a substrate bias voltage. CONSTITUTION:A CMOS circuit is formed of an N-channel MOSFETQ1 having N<+> type layers 3, 3' and a gate 4 of a P type semiconductor substrate 1, and a P channel MOSFETQ2 having an N<+> type layer 6, a P<+> type layers 7, 7 and a gate 8 formed on the main surface of an N-well 5 provided on the substrate 1. N-channel MOSFETs Q3, Q4 are formed of N<+> type layers 9, 9, 10, 10 and gates 11, 12 formed on the main surface of the substrate 1 and a rectifier 14 of a substrate bias generator 13 is formed by connecting a pair of the Q3, Q4 on the substrate 1. Since a substrate bias voltage VN2 outputted from the generator 13 is supplied to the substrate 1, the capacity of the CMOS made of Q1, Q2 is reduced to accelerate the operation, and the power consumption is reduced by the CMOS. |
