| 摘要 |
PURPOSE:To improve the converting speed by transferring sequentially a voltage held in a sample and hold circuit with an analog storage element so as to apply pipeline processing to digital value conversion. CONSTITUTION:In impressing an analog electric signal to the sample and hold circuit 11, the impressed voltage is held by a timing signal from a clock circuit 16. The output is transferred to an analog storage element group 12. Each output of the analog storage element group 12 is an input to an analog storage element of the next stage and inputted to a comparator group 13 in parallel. Then a signal of '1' or '0' being the result of comparison is inputted to an SAR of the next stage and fetched in the internal register group 14 at each timing of the clock. Thus, the feedback loop is constituted of the comparator group 13, the SAR group 14, a D/A converter group 15 to constitute a follow-up comparison type A/D converter. Since the data is applied with A/D conversion by pipeline processing while it is transferred to the analog storage element 12, the output digital signal is extracted at each timing of clock and the converting speed is quickened.
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