发明名称 CLAMPING CIRCUIT IN ANALOG/DIGITAL CONVERTER
摘要 PURPOSE:To attain a digital conversion with high stability and high dynamic range by controlling a conversion minimum grade level in an A/D converter at the optimum level. CONSTITUTION:A digital video signal from an A/D converter 2 is compared with the output of a clamp level setting circuit 16 at a comparator 15, and when the output of the A/D converter 2 is larger, signals of H and L are outputted respectively to AND gates 17 and 18. A clamp pulse from a clamp pulse generation circuit 19 is inputted to the AND gates 17 and 18, and either of analog switches 20 or 21 is turned on, and a voltage of positive polarity from a reference power source 22, or a voltage of negative polarity from a reference power source 23 is supplied to an estimating capacitor 26, and an electric charge is accumulated or discharged. The output voltage of the capacitor 26 is inputted to an adder circuit 11 through a buffer amplifier 27, and the lowest grade DC level of the video signal is decided.
申请公布号 JPS62164381(A) 申请公布日期 1987.07.21
申请号 JP19860004981 申请日期 1986.01.16
申请人 TOSHIBA CORP 发明人 HARADA TOYONARI
分类号 A61B6/00;H03M1/10;H04N5/18 主分类号 A61B6/00
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