| 摘要 |
PURPOSE:To obtain a CMOS gate circuit driven at a high speed, with less power consumption and offering high circuit integration by combining two CMOS transfer gates, a P-channel FET and an N-channel FET controlled by the same control signal. CONSTITUTION:With a control signal C1 at VCC level (H level) and a signal C1' at a VSS level (L level), P-channel FETQ5 and an N-channel FET Q6 are turned off, and two sets of CMOS transfer gates are turned on. Thus, an input signal A1 is inputted to gates of a P-channel FETQ7 and an N-channel FETQ8 as it is in this case, and the inverse of input signal A1 becomes an output signal B1. With the control signal C1 at L level and the signal C1' at H level, the two sets of CMOS transfer gates are turned off, the P-channel FETQ5 and the N-channel FETQ6 are turned on, both the P-channel FETQ7 and the N- channel FETQ8 are turned off and an output point 103 reaches a high impedance state. |
