发明名称 DATA PROCESSOR
摘要 PURPOSE:To attain high speed data transfer in an internal bus line by giving precharge to the internal bus line to an intermediate level of a power voltage in advance. CONSTITUTION:A precharge circuit PR consists of a P-channel MOSFET Q5 receiving a control signal phi'pr at its gate, a P-channel MOSFET Q6 of diode connection, an N-channel MOSFET Q7 whose gate receives a control signal phipr and an N-channel MOSFET Q8 of diode connection. In the stage of the instruction fetch, the control signals phi'pr, phipr are brought respectively into a low and a high level and the internal bus line BL is precharged in advance to the intermediate level. Thus, even when the size of a discharge MOSFET is not made large, the high speed discharge of the bus line is made possible, an undesired capacitive load of the internal bus line based on the discharge MOSFET is decreased and the high speed data transfer in the internal bus line is attained.
申请公布号 JPS62224119(A) 申请公布日期 1987.10.02
申请号 JP19860065738 申请日期 1986.03.26
申请人 HITACHI LTD 发明人 KIKUCHI AKIRA
分类号 H03K19/096;H03K19/017 主分类号 H03K19/096
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