发明名称 DATA DELAY CIRCUIT
摘要 <p>PURPOSE:To set a delay time with high accuracy and to realize the low cost of a data delay circuit, by providing a voltage variable power source which changes the gate delay element of a C-MOS, etc., and the power source voltage of the gate delay element arbitrarily. CONSTITUTION:The data write compensation circuit of a magnetic disk device is constituted of the data delay circuit 6, FFs 20-22, a write data separation circuit 9, and a 3-OR gate 18, and write data is written on a magnetic disk by a magnetic head, and the pattern peak shift of a readout waveform due to high density recording is compensated. The voltage variable power source 1 and the gate delay element 2 connected in (n) stages with the C-MOS, etc., are provided in the delay circuit 6, and when input data D1 is inputted by a power source voltage VCC, output data D0 delayed for a time (t) is outputted. And by changing the power source voltage VCC to a VCC+DELTAV or a VCC-DELTAV from the variable power source 1, the fine adjustment of the delay time of the delay element 2 to a (t') or a (t'') is performed, and set delay synchronizing signals 13 and 14 are outputted.</p>
申请公布号 JPS63247971(A) 申请公布日期 1988.10.14
申请号 JP19870077443 申请日期 1987.04.01
申请人 HITACHI LTD;HITACHI COMPUTER PERIPHERALS CO LTD 发明人 IWAI TAKEO;HARUNA TOSHIYUKI;TOKIDA YOSHINORI
分类号 G11B20/10;H03K5/13;H03K5/133;H03K5/134 主分类号 G11B20/10
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