Semiconductur memory device with redundant memory cell array.

摘要

There is disclosed a semiconductor memory device comprising a plurality of major memory cell blocks (32 to 39) divided into a plurality of sub-blocks (40 to 71), a redundant memory cell block (74) identical in size with each sub-block, write-in/sense amplifier circuits (118 to 126), two stages of selectors (76 to 108 and 109 to 116) operative to transfer data bits supplied from the respective major memory cell blocks and the redundant memory cell block to the write-in/sense amplifier circuits, a redundant information storage (136) for storing memory locations of defective major memory cells in one of the major memory cell block, and a shifting circuit (127) operative to replace the data bit read out from one of the defective major memory cells with the data bit read out from the redundant memory cell block on the basis of the memory location stored in the storage, and the number of the write-in/sense amplifier circuits is equal to the total number of the major memory cell blocks and the redundant memory cell block, so that the write-in/sense amplifier circuits consume a relatively small amount of area by virtue of the reduction in number.