| 摘要 |
<p>In a logic probe having the facility to detect logic pulses of shorter pulse width than a selected duration, a detected input pulse is delayed by the selected duration in a delay network (18) and fed to the D input of a D-type flip-flop (12). The undelayed logic pulse is fed to the CLK input. If the input pulse is a negative pulse and is longer than the delay time, the D input will be at logic zeero when the trailing edge of the undelayed pulse arrives at CLK and the flip-flop remains reset. If the delay is longer than the detected pulse the flip-flop will set and then be immediately reset by way of an inverter (20), producing a short pulse on its Q-BAR output, which is latched in a latch flip-flop (22). Positive pulses are similarly detected by flip-flops (24, 26). A microprocessor (30) polls the latch flip-flops, signals whenever a short pulse is detected, and its polarity, and then clears the latch.</p> |
