| 摘要 |
PURPOSE:To execute effective emulation even in a target system, in which a clock frequency is high, by providing a phase control circuit, which is composed of a divider and a phase comparator, etc., between an input buffer and an emulation CPU. CONSTITUTION:A phase control circuit 2 is provided between an input buffer 3 and an emulation CPU 1. In the circuit 2, an input clock 27 is divided into a frequency 1/2 by a frequency divider 21 and a reference clock 28 of a duty 50% is outputted to a phase comparator 22. After an output clock 30 is delayed for a constant time by a delaying circuit 26, it is divided into the frequency 1/2 by a frequency divider 25 and a comparing clock 29 is outputted to the comparator 22. In the comparator 22, the phases of the clocks 28 and 29 are compared and when the phase of the clock 29 proceeds to the clock 28, the oscillating frequency of a VCO 24 is lowered. When the phase of the clock 29 is delayed, the oscillating frequency is increased and the same phase as the clock 28 is obtained. Then, when a phase difference goes to be zero, the oscillating frequency is fixed. Thus, a clock frequency range, in which the emulation can be executed, can be extended. |
