发明名称 MANUFACTURE OF THIN FILM TRANSISTOR
摘要 <p>PURPOSE:To reduce parasitic capacity by a method wherein regions with a passivation layer and regions without the passivation layer are provided in a region, where a drain electrode and a gate electrode are piled up, along the length of the gate electrode. CONSTITUTION:Photoetching is applied for etching a passivation layer 24 into an island and patterning is so accomplished that there will be regions with the passivation layer 24 and regions without the passivation layer 24 along the length of a gate electrode 21. In this example, only the region nearer to a drain electrode 27 is divided into regions with or without the passivation layer 24. A similar design is also feasible wherein the region nearer to a source electrode is similarly divided, where the passivation layer 24 may be divided into a plurality of independent islands. In a device designed as such, a parasitic capacity CGD attributable to the overlapping of a gate electrode 7 and a drain electrode 11 may be reduced, which suppresses irregular or residual images from being generated.</p>
申请公布号 JPH01125867(A) 申请公布日期 1989.05.18
申请号 JP19870283503 申请日期 1987.11.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIYATA YUTAKA;KAWAMURA TETSUYA;TSUTSU HIROSHI;CHIKAMURA TAKAO
分类号 H01L27/12;G02F1/136;G02F1/1368;H01L29/78;H01L29/786 主分类号 H01L27/12
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