| 摘要 |
PURPOSE:To simplify the constitution of a multiplier by performing two- complement calculation by means of (m) selectors, (m) switching controller inverters, and m-input adder circuits with (m) carry inputs. CONSTITUTION:Selectors 200, 201, and 202 correspond respectively to term factors which do not become zero of multiplying factors and select the left shifting data of each multiplication input data by means of factor selecting signals SEL. Inverters 210, 211, and 212 execute data bit inversion when two- complement controlling signals IVT(1), IVT(2), and IVT(3) become '1' when the term factor of the multiplication factors corresponding to the selectors 200, 201, and 202 are '-1'. Simultaneously, '1' is inputted to carry inputs (CI) of adders 220, 221, and 222 and two-complement calculation is performed. At the same time, the adders 220, 221, and 222 add output data of the inverters 210, 211, and 212 and execute the multiplication of multiplication input data X by the multiplication factors. |
