| 摘要 |
<p>PURPOSE:To prevent the storage contents of a storage means from being destroyed by performing a control of the timing by which a reset signal is given based on the access of the storage means by a processor, for the processor, though a signal requesting a reset is generated from a reset circuit at any time. CONSTITUTION:A microprocessor unit 1 performs read/write of a dynamic RAM 3 via a dynamic RAM control unit 2. The output signal of a reset circuit 4 is given to a reset timing setting circuit 5. The reset timing setting circuit 5 gets a reset enable/inhibition signal from the dynamic control unit 2. When a reset enable/inhibition signal is set to a reset inhibition, a reset signal is not immediately outputted even if a reset request signal is given from the reset circuit 4 and the reset signal is given to the microprocessor 1 after waiting till a reset is enabled.</p> |
